How to programmatically create lumped port in inner PCB layer using PyAEDT?

maupaz92

Hi,

It is quite common for me to cut a design to extract a vertical transition, e.g. Layer1-to-Layer6, to understand crosstalk, return loss, etc. When working with many nets, assigning the ports takes 80-90% of the process. I'm trying to find a way to do this with PyAnsys.

I'm using a Hfss3dLayout object to get the nets and lines of a net, however, I haven't found a good way to assign the lumped port to the edge of the trace.

Any help would be appreciated.

Thanks.

svandenb-dev

Hi @maupaz92 ,

Actually you must use PyEDB which is a dependent package inside PyAEDT. You can use PyEDB from within PyAEDT or as standalone, it allows you to edit and manipulate directly EDB database to build ready to solve project in memory (e.g. no UI).

Beyond your question I think you need to get familiar with the package, I give you the online help link.

PyEDB architecture and design navigation — PyEDB